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標題: 基于Verilog的串口調試，在Modelsim中仿真正常，但在FPGA開發板上沒反應 [打印本頁]

作者: x1i2e3 時間: 2012-11-21 19:23
標題: 基于Verilog的串口調試，在Modelsim中仿真正常，但在FPGA開發板上沒反應
基于Verilog的串口調試，在Modelsim中仿真正常，但在FPGA開發板上用串口調試助手調試沒反應，麻煩高手指教一下。萬分感謝！

頂層文件
module ckdcwj(rst,clk,rxd,txd,data1,nclk);
input rst;
input clk;
input rxd;
output  txd;
inout [9:0] data1;
inout nclk;
wire  [9:0]  data1;
wire  nclk;
js_rxd u1(.rst(rst), .nclk(nclk), .rxd(rxd), .data1(data1));
fs_txd u2(.rst(rst), .nclk(nclk), .data1(data1), .txd(txd));
nclk u3(.clk(clk), .rst(rst), .nclk(nclk));
endmodule

接受模塊

module js_rxd(rst,nclk,rxd,data1);
input  rst;
input  nclk;
input  rxd;
output [9:0] data1;
reg  [3:0] count1;
reg  [3:0] count2;
reg [7:0] data;
reg  [3:0] cnt;
reg rec_reg1;
reg  rec_reg2;
reg  txdone=1'b1;
reg  [9:0]data1;
reg  [2:0] cunt=0;

parameter start=4'b0000,
      bit0=4'b1000,
bit1=4'b1001,
bit2=4'b1010,
bit3=4'b1011,
bit4=4'b1100,
bit5=4'b1101,
bit6=4'b1110,
bit7=4'b1111,
stop=4'b0010;


initial cnt<=start;
always  @(posedge nclk or negedge rst)
begin
  if(!rst)
  begin
cunt<=0;
rec_reg1<=1'b1;
  rec_reg2<=1'b1;
  data<=8'hzz;
  end
  else if(rec_reg1&&rec_reg2)
  begin
rec_reg1<=rxd;
  rec_reg2<=rec_reg1;
  end
  else if(!rec_reg1&&rec_reg2&&cunt==2)
  begin
  case(cnt)
  start:cnt<=bit0;
  bit0:begin
      if(count1)begin
         data[0]<=rxd;
         cnt<=bit1;
      end
else cnt<=bit0;
      end
  bit1:begin
      if(count1)begin
   data[1]<=rxd;
cnt<=bit2;
end
else cnt<=bit1;
end
  bit2:begin
      if(count1)begin
   data[2]<=rxd;
cnt<=bit3;
end
else cnt<=bit2;
end
bit3:begin
      if(count1)begin
   data[3]<=rxd;
cnt<=bit4;
end
else cnt<=bit3;
end
bit4:begin
      if(count1)begin
   data[4]<=rxd;
cnt<=bit5;
end
else cnt<=bit4;
end
bit5:begin
      if(count1)begin
   data[5]<=rxd;
cnt<=bit6;
end
else cnt<=bit5;
end
bit6:begin
      if(count1)begin
   data[6]<=rxd;
cnt<=bit7;
end
else cnt<=bit6;
end
bit7:begin
      if(count1)begin
   data[7]<=rxd;
cnt<=stop;
end
else cnt<=bit7;
end
stop:begin
   if(count1)begin
  if(txdone)
      begin
      data1<={1'b1,data[7:0],1'b0};
      cnt<=start;
  rec_reg1<=1'b1;
rec_reg2<=1'b1;
cunt<=0;
end
end
end
  default:begin
   data<=8'hzz;
  rec_reg1<=1'b1;
rec_reg2<=1'b1;
end
endcase
  end
  else  cunt<=cunt+1;
  end

always @(posedge nclk or negedge rst)
begin
if(!rst)
begin
  count1<=0;
  count2<=0;
  end
  else if(count2==7)
  begin
  count2<=0;
  count1<=1;
  end
else  begin
count1<=0;
count2<=count2+1;
end
end
  endmodule

發送模塊

module fs_txd(rst,nclk,data1,txd);
input rst;
input nclk;
input [9:0] data1;
output txd;
reg  [3:0] count1;
reg  [3:0] count2;
reg  txd;
reg  [3:0] count;
parameter start=4'b0000,
      wit0=4'b1000,
      wit1=4'b1001,
wit2=4'b1010,
wit3=4'b1011,
wit4=4'b1100,
wit5=4'b1101,
wit6=4'b1110,
wit7=4'b1111,
stop=4'b0001;
initial count<=start;
always @(posedge nclk or negedge rst)
begin
   if(!rst)
txd<=1'bz;
else if(!data1[0]) begin
case(count)
start:begin
      if(count1)begin
      txd<=data1[0];
      count<=wit0;
end
else count<=start;
      end
wit0:begin
      if(count1)begin
      txd<=data1[1];
      count<=wit1;
end
else count<=wit0;
end
wit1:begin
      if(count1)begin
      txd<=data1[2];
count<=wit2;
end
else  count<=wit1;
end
wit2:begin
      if(count1)begin
      txd<=data1[3];
count<=wit3;
end
else  count<=wit2;
end
  wit3:begin
      if(count1)begin
      txd<=data1[4];
count<=wit4;
end
else  count<=wit3;
end
  wit4:begin
      if(count1)begin
      txd<=data1[5];
count<=wit5;
end
else  count<=wit4;
end
wit5:begin
      if(count1)begin
      txd<=data1[6];
count<=wit6;
end
else count<=wit5;
end
wit6:begin
      if(count1)begin
      txd<=data1[7];
count<=wit7;
end
else count<=wit6;
end
wit7:begin
      if(count1)begin
      txd<=data1[8];
count<=stop;
end
else count<=wit7;
end
  stop:begin
      if(count1)begin
      txd<=data1[9];
   count<=start;
   end
   else  count<=stop;
   end
default:txd<=1'bz;
endcase
end
end

always @(posedge nclk or negedge rst)
begin
if(!rst)
begin
  count1<=0;
  count2<=0;
  end
  else if(count2==7)
  begin
  count2<=0;
  count1<=1;
  end
else  begin
count1<=0;
count2<=count2+1;
end
end
endmodule

波特率發生模塊

module nclk(clk,rst,nclk);
input  clk,rst;
output  nclk;
reg nclk;
reg [15:0]  cnt;
parameter yu_clk=50000000,
mu_clk=76800;
wire [15:0] step=yu_clk/mu_clk-1;
always @( clk or  rst)
begin
if(!rst)
begin
nclk<=0;
cnt<=0;
end
else if(cnt==step)
begin
nclk<=~nclk;
cnt<=0;
end
else
cnt<=cnt+1;
end
endmodule

仿真結果
[img]file:///C:/Users/Administrator/AppData/Roaming/Tencent/Users/1727445957/QQ/WinTemp/RichOle/NTSB%7DOD[K]U6~P@%60K_X_2IG.jpg[/img]

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