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標題: DSP5402之McBSP從設備SPI硬件四種模式配置實例(經過硬件測試) [打印本頁]

作者: HotTiDSP 時間: 2009-4-2 22:01
標題: DSP5402之McBSP從設備SPI硬件四種模式配置實例(經過硬件測試)
搜索"C5402def.h"看看~~~簡單明了~~~
雖然C5402cfg.h/c5402cfg.c"更強大，俺暫不想發布~~~

void McBSPObj::McBSP0Init(void)//McBSP從設備SPI硬件配置
{
/*-------------------------------------------------------------
  DSP5402之McBSP從設備SPI硬件四種模式配置實例(經過硬件測試)
--------------------------------------------------------------*/
//PCR設置過程(FSM=0,CLKM=0)
  McBSP0->SPSA = PCR;
  McBSP1->SPSD = (0 << PCR_XIOEN) //發送非通用I/O模式位
            | (0 << PCR_RIOEN) //接收非通用I/O模式位
            | (0 << PCR_FSXM)  //外部發送幀同步脈沖(外部片選)
            | (0 << PCR_FSRM)  //外部接收幀同步脈沖(外部片選)
            | (0 << PCR_CLKXM) //外部發送時鐘(外部時鐘源)
            | (0 << PCR_CLKRM) //外部接收時鐘(外部時鐘源)
#if SPIMODE == 0
//SPI設置過程00(0--FS高電平有效,0--CLK上升沿收發數據)

            | (0 << PCR_FSXP)  //發送幀同步脈沖極性(高電平有效)
            | (0 << PCR_FSRP)  //接收幀同步脈沖極性(高電平有效)
            | (0 << PCR_CLKXP) //發送時鐘極性(上升沿發送數據)
            | (0 << PCR_CLKRP);//接收時鐘極性(上升沿接收數據)
#endif
#if SPIMODE == 1
//SPI設置過程01(0--FS高電平有效,1--CLK下降沿收發數據)
            | (0 << PCR_FSXP)  //發送幀同步脈沖極性(高電平有效)
            | (0 << PCR_FSRP)  //接收幀同步脈沖極性(高電平有效)
            | (1 << PCR_CLKXP) //發送時鐘極性(下降沿發送數據)
            | (1 << PCR_CLKRP);//接收時鐘極性(下降沿接收數據)
#endif
#if SPIMODE == 2
//SPI設置過程10(1--FS低電平有效,0--CLK上升沿收發數據)
            | (1 << PCR_FSXP)  //發送幀同步脈沖極性(低電平有效)
            | (1 << PCR_FSRP)  //接收幀同步脈沖極性(低電平有效)
            | (0 << PCR_CLKXP) //發送時鐘極性(上升沿發送數據)
            | (0 << PCR_CLKRP);//接收時鐘極性(上升沿接收數據)
#endif
#if SPIMODE == 3
//SPI設置過程11(1--FS低電平有效,1--CLK下降沿收發數據)
            | (1 << PCR_FSXP)  //發送幀同步脈沖極性(低電平有效)
            | (1 << PCR_FSRP)  //接收幀同步脈沖極性(低電平有效)
            | (1 << PCR_CLKXP) //發送時鐘極性(下降沿發送數據)
            | (1 << PCR_CLKRP);//接收時鐘極性(下降沿接收數據)
#endif
//MCR1設置過程(RMCM=0)
  McBSP0->SPSA = MCR1;//
  McBSP0->SPSD = (0 << MCR1_RMCM) //允許接收多通道選擇(0)
            | (0x00 << MCR1_RPBBLK)
            | (0x00 << MCR1_RPABLK)
            | (0x00 << MCR1_RCBLK);
//MCR2設置過程(XMCM=0)
  McBSP0->SPSA = MCR2;//
  McBSP0->SPSD = (0x00 << MCR2_XMCM) //允許發送多通道選擇(00b)
            | (0x00 << MCR2_XPBBLK)
            | (0x00 << MCR2_XPABLK)
            | (0x00 << MCR2_XCBLK);

//RCERA設置過程
  McBSP0->SPSA = RCERA;//
  McBSP0->SPSD = 0;

//RCERB設置過程
  McBSP0->SPSA = RCERB;//
  McBSP0->SPSD = 0;

//XCERA設置過程
  McBSP0->SPSA = XCERA;//
  McBSP0->SPSD = 0;

//XCERB設置過程
  McBSP0->SPSA = XCERB;//
  McBSP0->SPSD = 0;

//XCR1設置過程
  McBSP0->SPSA = XCR1;//
  McBSP0->SPSD = (0x00 << XCR1_XFRLEN1) //每幀1個字(每幀中斷的次數1!!!)
//             | (0x02 << XCR1_XWDLEN1);//每字16位長(每次中斷的字節數2!!!)
            | (0x00 << XCR1_XWDLEN1);//每字8位長(每次中斷的字節數2!!!)
//XCR2設置過程
  McBSP0->SPSA = XCR2;
  McBSP0->SPSD = (0 << XCR2_XPHASE) //單相幀(其他設置都為0)
            | (0x00 << XCR2_XCOMPAND)//發送數據從最高位(MSB)開始
            | (0x00 << XCR2_XDATDLY);//同步后延遲0位數據
//RCR1設置過程
  McBSP0->SPSA = RCR1;
  McBSP0->SPSD = (0x00 << RCR1_RFRLEN1) //每幀1個字(每幀中斷的次數1!!!)
//             | (0x02 << RCR1_RWDLEN1);//每字16位長(每次中斷的字節數2!!!)
            | (0x00 << RCR1_RWDLEN1);//每字8位長(每次中斷的字節數2!!!)
//RCR2設置過程
  McBSP0->SPSA = RCR2;
  McBSP0->SPSD = (0 << RCR2_RPHASE) //單相幀(其他設置都為0)
            | (0x00 << RCR2_RCOMPAND)//接收數據從最高位(MSB)開始
            | (0x00 << RCR2_RDATDLY);//同步后延遲0位數據
//SRGR1設置過程
  McBSP0->SPSA = SRGR1;
  McBSP0->SPSD = (0x00 << SRGR1_CLKGDV);//1
//SRGR2設置過程
  McBSP0->SPSA = SRGR2;
  McBSP0->SPSD = (0 << SRGR2_FSGM)
            | (1 << SRGR2_CLKSM)//由CPU時鐘產生的采樣率時鐘1
            | (0 << SRGR2_CLKSP)//0
            | (1 << SRGR2_GSYNC)//
            | (0x0f << SRGR2_FPER);//0x0f
//SPCR1設置過程(CLKSTP=1Xb,RINTM=00b)
  McBSP0->SPSA = SPCR1;
  McBSP0->SPSD = (0x00 << SPCR1_RINTM)  //接收中斷模式00(每幀接收1次中?
                           | (0 << SPCR1_DLB)    //禁止回送
            | (1 << SPCR1_DXENA)    //DX使能
            | (0x00 << SPCR1_RJUST)  //接收符號不擴展
            | (0x02 << SPCR1_CLKSTP);//SPI模式時鐘開始于上升沿（無延遲）
//SPCR2設置過程(XINTM=02b)
  McBSP0->SPSA = SPCR2;
  McBSP0->SPSD = (0x02 << SPCR2_XINTM)//發送中斷模式02
            | (1 << SPCR2_XEMPTY)  //發送移位寄存器空
            | (1 << SPCR2_XRDY); //發送準備好
//SPCR1復位過程
  McBSP0->SPSA = SPCR1;
  McBSP0->SPSD|= (1 << SPCR1_RRST);//接收器復位
//SPCR2復位過程
  McBSP0->SPSA = SPCR2;
  McBSP0->SPSD|= (1 << SPCR2_XRST)//發送器復位
            | (1 << SPCR2_GRST)//采樣率發生器復位
            | (1 << SPCR2_FRST);//幀同步發生器復位
//清除允許BXINT0中斷過程
//  SREG->IFR = (1 << IFR_BXINT0);//清除BXINT0中斷標志
//  SREG->IMR |= (1 << IMR_BXINT0);//允許BXINT0中斷
//清除允許BRINT0中斷過程
  SREG->IFR = (1 << IFR_BRINT0);//清除BRINT0中斷標志
  SREG->IMR |= (1 << IMR_BRINT0);//允許BRINT0中斷
}

void McBSPObj::McBSP1Init(void)//GPIO配置
{
  McBSP1->SPSA = SPCR1;
  McBSP1->SPSD = 0;
  McBSP1->SPSA = SPCR2;
  McBSP1->SPSD = 0;
  McBSP1->SPSA = PCR;
//設置收發為IO接口,DX輸出,DR,CLKS輸入
  McBSP1->SPSD = (1 << PCR_RIOEN) //通用I/O模式位
//硬件RDDOG喂狗信號(BDX1)管腳輸出模式默認I/O設置
            | (1 << PCR_XIOEN) //通用I/O模式位
//硬件RD SIA信號(BFSR1)管腳輸入模式設置
            | (0 << PCR_FSRM) //FSR為輸入IO
//硬件FM CE信號(BFSX1)管腳輸出模式設置
            | (1 << PCR_FSXM) //FSR為輸出IO,FLASH的片選信號
//硬件FM CE信號(BFSX1)管腳高電平輸出控制
            | (1 << PCR_FSXP) //關閉FLASH的片選信號(FSX=1)
            | (0 << PCR_CLKRM) //CLKR為輸入IO
            | (0 << PCR_CLKXM);  //CLKX為輸入IO,CLKX信號
}

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