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【獵頭職位:北京/上海需要若干位 Senior Staff SOC Design Engineer(Low Power)】聯(lián)系人：David-Chen，郵箱：hr@kthr.com，微信也可查詢職位啦！打開(kāi)手機(jī)微信，搜號(hào)碼“KTHR_COM”或查找微信公眾帳號(hào)“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ 職位描述： Work closely with the software, hardware and IP team to plan the chip clock architecture and low power proposal. Define chip low power scenario and the related condition. Write and validate the CPFUPF file for chip power description Define and develop the verification cases for chip low power design with the verification team. Provide the sample code to software team for low power integration. Provide the clock SDC for synthesis team. Power estimation before chip TO, power breakdown and analysis after chip back. Script development for chip low power related automation. Interact with external IP teamsvendors to resolve all technical implementation and integration issues. Work closely with STA team and PD to for timing closure. 任職資格： MSBS in EECS (MS preferred). Minimum 5 years of experience with MSEECS or 7 years with BSEECS. Familiar with ASIC development, especially logic design, RTL coding, verification, synthesis, timing closure and physical design flow. Proficient in advanced SOC low power design techniques, hands-on clock and PMU design, integration, verification, CPFUPF script development. One or more advantages of the followings are highly desirable Strong background in synthesis, scan and memory BIST; analog IP design and test, especially high speed Serdes test such as (MIPI, LVDS, USB3.0…; digital communication, CPU and networking protocols; Experiences with ARMDSP, AHBAXI bus, NoC and peripheral (PCIeUSB) development. Excellent teamwork, interpersonal and communication skills. Fluent in Chinese and English both verbal and written. Scriptingprogramming skill in CC++, Tcl, PerlCsh desired. Ability to work in stressful situations with tight schedules to meet. |
