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【獵頭職位:上海需要若干位 Senior Staff SOC Design Engineer(Low Power)】聯(lián)系人：David-Chen，郵箱：hr@kthr.com，微信也可查詢職位啦！打開(kāi)手機(jī)微信，搜號(hào)碼“KTHR_COM”或查找微信公眾帳號(hào)“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ 工作內(nèi)容職位描述： 根據(jù)DE提供的RTL,release符合要求的網(wǎng)表文件以及相應(yīng)的約束文件,并且協(xié)助PR team timing signoff.具體工作包括 synthesis, DFT, formal check，low power check, SDC generation, STA signoff. 任職資格： 1. 電子工程,微電子，半導(dǎo)體以及相關(guān)領(lǐng)域的本科碩士博士。 2. 需要5年以下工作經(jīng)驗(yàn)： Proficiency in all following technology logic synthesis ,DFT,formal check and STA expert for at least one area, such as timing , DFT, power, signoff. Proficiency in related EDA tools. Proficiency in Verilog language. Experience with logic design and simulation. Experience with 40nm or 28nm process is a plus. Good knowledge of SOC design is a plus. Self-motivated and good team player. |
