|
NO.400-【獵頭職位：西安需要多位 Design Verification Engineer】聯(lián)系人：Sophie-Song,郵箱：hr@kthr.com，微信也可查詢職位了！打開手機(jī)微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ 崗位職責(zé)： 1、Participate ASIC digital verification for various IP/SoC projects; 2、Create verification plans and execution; 3、Develop virtual prototype modeling for algorithm logic; 4、Develop DV architecture and verification environment; 5、Verification execution and sign-off. 崗位要求： 1、Excellent team working style; 2、Solid IP/SoC verification background; 3、Experience with IP/SoC sign-off; 4、Master with 2+ years working experiences on ASIC digital verification; 5、Production experiences on verification strategies and vPlan extraction and execution; 6、Familiar with SystemVerilog/UVM for testbench creation, debug, reuse, constrained-random stimulus and functional coverage; 7、CXL / DSP experience is an advantage; 8、Direct test at SoC level is a must, low level driver awareness is an advantage; 9、Project experiences on ARM buses, such as AXI/AMBA/APB is an advantage; 10、Familiar with verification tools; 11、Familiar with Linux, csh/Python or any script languages; 12、Good English skills (read and write); Additionally: 13、Having crypto(e.g. ECC, AES, RSA, SM2/3/4, TRNG…) knowledge is a plus; 14、Typical serial bus experiences, e.g. I2C, I3C, SMBus protocol knowledge is a plus. 福利：五險一金 補(bǔ)充醫(yī)療保險 員工旅游 績效獎金 年終獎金 彈性工作 
|
