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【獵頭職位：上海需要一位“Talent Development Supervisor”】關(guān)鍵詞：Training, HR,Talent Development，聯(lián)系人：Julie Zhou，郵箱: julie-zhou@kthr.com，QQ: 1873647643，微信也可查詢職位啦！打開手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ Job Description 1. Conduct annual training needs survey implementation, analysis and form annual training plan 2.Annual training plan’s implementation, maintenance, evaluation and enhancement 3.Global training and development program roll out in Asia Pacific 4.Effective use of Learning Management System to communicate training calendar, assignment to target group, as well as optimal the system based on requirements 5.Review and update learning portfolio and delivery approach to maximize effectiveness and increase value to business 6.In charge of new hire orientation from training, feedback collection and enhancement 7.Training related policies maintenance to ensure it’s up to date 8.Responsible for delivering basic training courses such as supervisory courses, interpersonal skills training and culture driven program 9.Competency based curriculum implementation and evaluation Qualification 1.At least 8 years of working experience, prefer with 1-2 years of people management experience 2.Bachelor's Degree or above, certified Trainerqualification. 3.Good interpersonal and withcross functional coordination skill. 4.Good problem solving, analytical skills, detail-orientated. 5.Demonstrate people management skill eg. Coaching, delegation, 6.Semiconductor manufacturing industry experiences preferred. 7.Excellent English speaking, reading and writing capabilities. 【獵頭職位：香港需要一位“Senior Digital Design Engineer”】關(guān)鍵詞：Digital design, Verilog,SoC and embedded system,Perl, TCL and Make，聯(lián)系人：Judy Wu，QQ:782288610，Email: judy-wu@kthr.com ，微信也可查詢職位啦！打開手機微信，搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ Responsibilities: 1.Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis 2.Develop verification environment and coverage closure 3.Support wafer level testing and silicon evaluation 4.Prepare technical documents Requirements: 1.B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage 2.5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations 3.Knowledge of SoC and embedded system. 4.Knowledge of scripting languages such as Perl, TCL and Make 5.Candidate with less experience will be considered as Digital Design Engineer 
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